A switching converter regulates power supplied to a load by modulating the duty ratio of a power switch that connects the power from a source to the load. The circuit diagram of a prior art step-down switching converter circuit without maximum duty control is depicted in FIG. 1. The prior art converter shown in FIG. 1 comprises a pair of switches Q1 and Q2 connected in series between an input voltage VIN and a ground node GND. A phase node 107 of switches Q1 and Q2 is simultaneously connected to a first end of an inductor L and to a current sense network 101, which generates a current signal ISNS indicative of the current through inductor L when the high-side switch Q1 is turned on. The current signal ISNS is then connected to a summation network 108 wherein ISNS is combined with a slope signal ISLOPE generated from a slope signal generator 110 to produce a combined current signal ISLOPE+SNS. A second end of inductor L is connected to an output node 111 having an output voltage VOUT. The output node is further connected to a load network 102 and a voltage divider formed by resistors R1 and R2. The voltage divider produces a feedback voltage VFB indicative of VOUT. VFB and a reference voltage VREF are connected respectively to the inverting input and the noninverting input of an error amplifier 104. The error amplifier 104 compares VFB to VREF and amplifies their difference. A compensation network 103, such as a Type II network formed by passive elements R3, C1, and C2, is connected to the output of the error amplifier 104, thereby generating an error signal VCOMP. VCOMP and a voltage signal VSUM indicative of ISLOPE+SNS are respectively connected to the inverting input and the noninverting input of a pulse width modulation (“PWM”) comparator 105, which compares VCOMP to VSUM and generates an output signal RESET. RESET and a clock signal CLK are respectively connected to the R input and the S input of a reset-dominant latch 106, which outputs a DUTY signal that is provided to a gate driver GD 109. The gate driver GD 109 generates HS and LS signals to control the switching frequency of switches Q1 and Q2, thereby achieving the regulation of power supplied to the load network 102.
FIG. 2 is a waveform diagram for the prior art converter shown in FIG. 1 wherein the voltage of VIN, VOUT, VCOMP, and VSUM are plotted versus time. In each switching cycle, the control signal VSUM starts at a base voltage VSUM0 at the base of the slope and increases at an approximately constant slew rate. As VSUM rises to the same voltage as VCOMP, which serves as a ceiling, VSUM resets to its initial voltage VSUM0 and repeat the slope cycle. During a typical switching cycle, the relationship between the switching frequency, the slew rate of VSUM, and VCOMP is expressed in EQ. (1), wherein FS is the switching frequency, TS is the switching period, m is the slew rate, and VSUM0 is the base voltage of VSUM.
                              F          S                =                              1                          T              S                                =                      m                          (                                                V                  COMP                                -                                  V                                      SUM                    ⁢                                                                                  ⁢                    0                                                              )                                                          EQ        .                                  ⁢                  (          1          )                    
FIG. 2 is partitioned into three temporal phases to elucidate the problem encountered by the prior art converter when the input-output voltage differential (i.e., the difference between VIN and VOUT) temporarily falls below the dropout voltage VTHRESHOLD. In Phase I, VIN, VOUT, and VCOMP are in their respective steady state conditions when the input-output voltage differential is greater than the dropout voltage VTHRESHOLD. The switching frequency of the converter in Phase I can be characterized by EQ. (2), wherein FS1, TS1, and VCOMP1 are, respectively, the switching frequency, the switching period, and VCOMP in Phase I. The voltage of slope signal VSUM starts from the base voltage VSUM0, increases to VCOMP1, then resets back to VSUM0. Operation in this manner repeats every TS1 second and maintains a switching frequency of FS1 until VCOMP changes.
                              F                      S            ⁢                                                  ⁢            1                          =                              1                          T                              S                ⁢                                                                  ⁢                1                                              =                                    1                              (                                                                            V                                              COMP                        ⁢                                                                                                  ⁢                        1                                                              -                                          V                                              SUM                        ⁢                                                                                                  ⁢                        0                                                                              m                                )                                      =                          m                                                V                                      COMP                    ⁢                                                                                  ⁢                    1                                                  -                                  V                                      SUM                    ⁢                                                                                  ⁢                    0                                                                                                          EQ        .                                  ⁢                  (          2          )                    
In Phase II, over the period from t1 to t3, VIN falls from the initial steady state voltage to below the target voltage for VOUT. At time t2, VOUT begins to decrease as the input-output voltage differential falls below the dropout voltage VTHRESHOLD. The drop in VOUT triggers a compensation response in which VCOMP rises to increase VOUT to its initial target voltage. However, since VOUT cannot exceed VIN, VOUT is prevented from attaining the target voltage when VIN is lower than the target voltage. While VOUT is lower than the target voltage, VCOMP continues to increase until it saturates, at which point VCOMP levels out. As previously mentioned, VCOMP provides the upper threshold for triggering VSUM to reset; increasing VCOMP causes VSUM to slope up unrestricted until it also saturates.
From time t4 to t6, VIN is gradually restored to its initial steady-state value. As VIN increases, the input-output voltage differential and VOUT also begin to increase. At tS, the input-out voltage differential exceeds VTHRESHOLD, at which point VOUT is restored to its target voltage. In response to the increase in VOUT, VCOMP gradually decreases until a new steady-state value is achieved at time t7. When VCOMP decreases to the same voltage as VSUM, the slope signal VSUM resets and resumes the aforementioned slope and reset cycle.
In Phase III, both VIN and VOUT are restored to their original steady-state voltage. VCOMP levels out to a new steady-state voltage VCOMP3, which may be different from the initial steady-state voltage VCOMP1. The switching frequency of the converter in Phase III can be characterized by EQ. (3), wherein FS3, TS3, and VCOMP3 are, respectively, the switching frequency, the switching period, and VCOMP in Phase III.
                              F                      S            ⁢                                                  ⁢            3                          =                              1                          T                              S                ⁢                                                                  ⁢                3                                              =                                    1                              (                                                                            V                                              COMP                        ⁢                                                                                                  ⁢                        3                                                              -                                          V                                              SUM                        ⁢                                                                                                  ⁢                        0                                                                              m                                )                                      =                          m                                                                    V                                          COMP                      ⁢                                                                                          ⁢                      3                                                        -                                      V                                          SUM                      ⁢                                                                                          ⁢                      0                                                                      ⁢                                                                                                                          EQ        .                                  ⁢                  (          3          )                    
Since the slew rate of VSUM is approximately constant and VCOMP provides the upper threshold for triggering VSUM to reset the slope cycle, the duration of each slope cycle depends on the difference between VCOMP and VSUM0. The greater the difference between VCOMP and VSUM0, the longer VSUM would take to reach the VCOMP threshold. It was previously introduced in EQ. (1) that the switching period TS is the inverse of the switching frequency FS. When a change in Wow causes the switching period TS to change, the switching frequency FS also changes. By way of example, assume that VSUM0 is 0 and that VCOMP3=2VCOMP1; then the relationship between the switching frequencies FS1 and FS3, can be derived by algebraic manipulation of EQs. (2) through (5). Substituting EQs. (2) and (4) into EQ. (6), it is determined that the switching frequency is reduced by half when VCOMP is doubled.
                              V                      SUM            ⁢                                                  ⁢            0                          =        0                            EQ        .                                  ⁢                  (          4          )                                                  V                      COMP            ⁢                                                  ⁢            3                          =                  2          ⁢                      V                          COMP              ⁢                                                          ⁢              1                                                          EQ        .                                  ⁢                  (          5          )                                                  F                      S            ⁢                                                  ⁢            3                          =                              m                          V                              COMP                ⁢                                                                  ⁢                3                                              =                                    m                              2                ⁢                                  V                                      COMP                    ⁢                                                                                  ⁢                    1                                                                        =                                          1                2                            ⁢                              F                                  S                  ⁢                                                                          ⁢                  1                                                                                        EQ        .                                  ⁢                  (          6          )                    
The above example demonstrates that the switching frequency of the prior art converter is dependent on VCOMP. The tendency for the switching frequency to drift after the circuit experiences a temporary anomalous decrease in the input voltage renders this prior art converter unsuitable for applications where the maintenance of a constant switching frequency is desirable or even essential.